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DATA SHEET
MOS INTEGRATED CIRCUIT
PD3720A
2700 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
The PD3720A is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD3720A has 3 rows of 2700 pixels and 3 pairs of 2 rows of 1350-bit charge transferred registers, reset feedthrough level clamp circuits, clamp pulse generation circuit and voltage amplifiers. It is suitable for color image scanners, color facsimiles and so on.
FEATURES
* Valid photocell * Line spacing * Color filter * Resolution : 2700 pixels x 3 : 42 m (4 lines) Red line-Green line, Green line-Blue line : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx*hour) : 12 dot/mm A4 (210 x 297 mm) size (shorter side) 300 dpi US letter (8.5" x 11") size (shorter side) * Drive clock level : CMOS output under 5 V operation * Data rate * Power supply * On-chip circuits : 3 MHz MAX. : +12 V : Reset feed-through level clamp circuits Clamp pulse generation circuit Voltage amplifiers * Pin assign : Compatible with the PD3720 * Photocell's pitch : 10.5 m
ORDERING INFORMATION
Part Number Package CCD linear image sensor 22-pin plastic DIP (400 mil)
PD3720ACY
The information in this document is subject to change without notice. Document No. S12035EJ1V0DS00(1st edition) Date published November 1996 N Printed in Japan
(c)
1996
PD3720A
COMPARISON CHART
Item PIN CONFIGURATION ELECTRICAL CHARACTERISTICS TIMING CHART Pin 11 Output fall delay time TYP. (ns) Output signal waveform
PD3720A
Analog ground 70
PD3720
Digital ground 80
Spike noise reduced
-
BLOCK DIAGRAM
VOD 19 AGND 2 AGND 11
2L 1
17
14
CCD analog shift register Transfer gate
S2699 S2700
13
D65 D66 D67
VOUT1 (B)
D14
S1
21
S2
........
D64
Photocell
TG1
Transfer gate CCD analog shift register
CCD analog shift register Transfer gate
S2699 S2700 D14 D64 D65 D66
12
D67
VOUT2 (G)
S1
S2
22
........
Photocell
TG2
Transfer gate CCD analog shift register Clamp pulse generator CCD analog shift register Transfer gate
S2699 S2700
10
D65 D66 D67
VOUT3 (R)
D14
S1
S2
1
........
D64
Photocell
TG3
Transfer gate CCD analog shift register
3
RB
4
1L
9
2
2
PD3720A
PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin plastic DIP(400 mil)
Output signal 3 (RED)
VOUT3
1
22
VOUT2
Output signal 2 (GREEN)
Analog ground
AGND
2
1 1 1
21
VOUT1
Output signal 1 (BLUE)
Reset gate clock
RB
3
20
NC
No connection
Last stage shift register clock 1
1L
4
19
VOD
Output drain voltage
No connection
NC
5
18
NC
No connection
No connection
NC
6
G R B
17
2L
Last stage shift register clock 2
No connection
NC
7
16
NC
No connection
No connection
NC
8
15
NC
No connection
Shift register clock 2
2
9
14
1
Shift register clock 1
2700
2700
2700
Transfer gate clock 3
TG3
10
13
TG1
Transfer gate clock 1
Analog ground
AGND
11
12
TG2
Transfer gate clock 2
PHOTOCELL STRUCTURE DIAGRAM
7.5 m
10.5 m
3 m
Channel stopper
Aluminum shield
3
PD3720A
ABSOLUTE MAXIMUM RATINGS (TA = +25 C)
Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Transfer gate clock voltage Operating ambient temperature Storage temperature VOD V1, V2, V1L, V2L VRB VTG1 - VTG3 TA Tstg Symbol Ratings -0.3 to +15 -0.3 to +15 -0.3 to +15 -0.3 to +15 -25 to +60 -40 to +70 Unit V V V V C C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 C)
Parameter Output drain voltage Shift register clock signal high level Shift register clock signal low level Reset gate clock high level Reset gate clock low level Transfer gate clock high level Transfer gate clock low level Data rate VOD V1H, V2H, V1LH, V2LH V1L, V2L, V1LL, V2LL VRBH VRBL VTG1H - VTG3H VTG1L - VTG3L fRB Symbol MIN. 11.4 4.5 -0.3 4.5 -0.3 4.5 -0.3 - TYP. 12.0 5.0 0 5.0 0 5.0 0 1 MAX. 12.6 5.5 +0.5 5.5 +0.5 5.5 +0.5 3 Unit V V V V V V V MHz
4
PD3720A
ELECTRICAL CHARACTERISTICS
TA = +25 C, VOD = 12 V, fRB = 1 MHz, data rate = 1 MHz, storage time = 5 ms, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p
Parameter Saturation voltage Saturation exposure Red Green Blue Photo response non-uniformity Average dark signal Dark signal non-uniformity Power consumption Output impedance Response Red Green Blue Image lag Offset level Note1 Output fall delay time Note2 Total transfer efficiency
Symbol Vsat SER SEG SEB PRNU ADS DSNU PW ZO RR RG RB IL VOS td TTE
Test Conditions
MIN. 2.0
TYP. 3.0 0.15 0.16 0.27
MAX. -
Unit V lx*s lx*s lx*s
VOUT = 1 V Light shielding Light shielding
6 0.5 1.5 400 0.5 14.14 12.95 7.77 20.20 18.50 11.10 2 3 4.5 70 92 98
20 2.5 8.0 600 1 26.26 24.05 14.43 10 6.6
% mV mV mW k V/lx*s V/lx*s V/lx*s % V ns %
VOUT = 1 V
VOUT = 1 V VOUT = 1 V, data rate = 3 MHz VOUT = 1 V
Register imbalance Response peak Red Green Blue Dynamic range
RI
0
1.0 630 540 460
4.0
% nm nm nm times times
DR1 DR2
Vsat /DSNU Vsat / Light shielding Light shielding -1000 -
2000 3000 -300 1.0 +300 -
Reset feed-through noise Note1 Random noise
RFTN
mV mV
Notes 1. Refer to TIMING CHART2. 2. When each fall delay time of 1L and 2L (t2, t1) is the TYP. value (refer to TIMING CHART 2).
5
PD3720A
INPUT PIN CAPACITANCE
Parameter Transfer gate clock pin capacitance Symbol CTG Pin name Pin No. 13 12 10 3 4 17 14 9 MIN. TYP. 200 200 200 50 30 30 700 700 MAX. Unit pF pF pF pF pF pF pF pF
TG1 TG2 TG3
Reset gate clock pin capacitance Last stage shift register clock pin capacitance
CRB CL
RB 1L 2L
Shift register clock pin capacitance 1 Shift register clock pin capacitance 2
C1 C2
1 2
6
PD3720A
TIMING CHART 1 (for each color)
TG1 to TG3 1 2 1L 2L RB
2763 2764 2765 2766 2767 2768 2769 10 11 12 13 14 15 16 61 62 63 64 65 66 1 2 3 4 5 6 7 8 9
1
2
3
4
5
6
7
VOUT1 to VOUT3
8
Optical black (49 pixels)
Valid photocell (2700 pixels) Invalid photocell (2 pixels) Invalid photocell (3 pixels)
TIMING CHART 2 (for each color)
t1 t2
1
90 % 10 % 90 % 10 %
2
1L
90 % 10 % 90 % t5 t3 t6 10 % t4 90 % 10 %
t1'
t2'
2L
td
RB
+ RFTN 90 % VOUT 10 % VOS - RFTN
7
PD3720A
TG1 to TG3, 1, 2 TIMING CHART
t7 90 % 10 % t9 90 % t11 t8
t10
TG
1
2
Symbol t1, t2 t1, t2 t4 t3 t5, t6 t7, t8 t9, t11 t10
MIN. 0 0 130 20 0 0 900 3000
TYP. 50 5 300 150 50 50 1000 10000
MAX. - - - - - - - -
Unit ns ns ns ns ns ns ns ns
1, 2 cross points 1
1L, 2 cross points 2
2 V or more
2 1, 2L cross points 1
2 V or more
1L
2 V or more
0.5 V or more
2 V or more
2L
0.5 V or more
Remark
Adjust cross points (1, 2), (1L, 2) and (1, 2L) with input resistance of each pin.
8
PD3720A
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time(s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.
PRNU (%) =
x x 100 x x : maximum of xj - x
2700 j=1
xj
2700
x=
xj : Output voltage of valid pixel number j
VOUT
x Register Dark DC level x
4.
Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
2700 j=1
dj
2700 dj : Dark signal of valid pixel number j
ADS (mV) =
9
PD3720A
5.
Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV): maximum of | dj - ADS |
j = 1 to 2700
dj: Dark signal of valid pixel number j
VOUT ADS Register Dark DC level DSNU
6.
Output impedance: ZO Impedance of the output pins viewed from outside.
7.
Response: R Output voltage divided by exposure (Ix*s). Note that the response varies with a light source (spectral characteristic).
8.
Image Lag: IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light ON OFF
VOUT V1 VOUT
V1 IL (%) = VOUT
x100
10
PD3720A
9. Register Imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels.
n 2
2 n RI (%) =
(V2j
j=1
-1
- V2j) x 100
1 n
Vj
j=1
n
n : Number of valid pixels Vj : Output voltage of each pixel 10. Random noise: Random noise is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding).
100
=
(Vi - V)
i=1
2
, V=
1
100
100
100 i=1
Vi
Vi : A valid pixel output signal among all of the valid pixels for each color
VOUT
V1 V2
...
line 1 line 2
...
V100
line 100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
11
PD3720A
STANDARD CHARACTERISTIC CURVES (TA = +25 C)
DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 2
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC
4
Relative Output Voltage Relative Output Voltage
1
2
1
0.5
0.25
0.2
0.1 0
10
20
30
40
50
0.1
1
5 Storage Time (ms)
10
Operating Ambient Temperature TA(C)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter) 100 B R
80
G
Response Ratio (%)
60
40
20
G B
0 400
500
600 Wavelength (nm)
700
800
12
PD3720A
APPLICATION CIRCUIT EXAMPLE
+12 V
10 + B3 1 2
RB
VOUT3
VOUT2
22
B2 B1
0.1 F 47 F/25 V
AGND
RB 1L
VOUT1 NC VOD NC
2L
21 20 19 18
47 47
3 4 5 6 7 8
NC NC NC NC
2 TG3
17
47
NC 16 NC
1 TG1 TG2
15
2
9 10 10 11
14 13 12 10 10
1 TG
AGND
B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 CCD VOUT 100 47 F/25 V
2SC945
2 k
Remark
Inverters : PD74HC04
13
PD3720A
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 22PIN PLASTIC DIP (400 mil)
(Unit : mm) 1bit 0.50.3
37.5 44.00.3
9.250.3
2.0
10.16
(1.79)
2.550.2 1 1.020.15 0.460.1 25.4 2.54 (5.42) 4.210.5 4.390.4
0 10
0.25
0.05
Name Plastic cap
Dimensions 42.9 x 8.35 x 0.7
2
Refractive index 1.5
1 The bottom of the package
The surface of the chip
2 The thickness of the cap over the chip 22C-1CCD-PKG6
14
PD3720A
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E). Type of Through-hole Device
PD3720ACY: CCD linear image sensor 22-pin plastic DIP (400 mil)
Process Wave soldering (only to leads) Partial heating method Conditions Solder temperature: 260 C or below, Flow time: 10 seconds or less. Pin temperature: 260 C or below, Heat time: 10 seconds or less (per each lead).
Caution For through-hole device, the wave soldering process must be applied only to leads, and make sure that the package body dose not get jet soldered. During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact.
15
PD3720A
NOTES ON CLEANING THE PLASTIC CAP
1 CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches. The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used.
2 RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent.
Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone
Symbol EtOH MeOH IPA NMP
16
PD3720A
[MEMO]
17
PD3720A
[MEMO]
18
PD3720A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
19
PD3720A
[MEMO]
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

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